RF front-end module integration design process based on Virtuoso and NI AWR software

　　Evolving communication standards such as LTE-A and 5G are driving innovation in RF architectures, posing challenges for RF front-end module design in terms of miniaturization, performance, and technical support for improving data throughput through improved spectrum efficiency.

　　To meet the demands for higher performance and smaller component sizes in multi-mode and multi-frequency phones, the industry is shifting module integration strategies from similar building blocks in a single package to multi-tech-based multifunctional front-ends. These developments target each frequency range, based on a single fully integrated RF module product, including multi-mode/multi-frequency power amplifiers (PAs), duplexers, and RF switches.

　　Typically, module and subsystem designers use a variety of techniques in their designs. These technologies include gallium arsenide (GaAs) and gallium nitride (GaN) monolithic microwave integrated circuits (MMICs), silicon RFICs, and multilayer laminates. Each technology is encapsulated in a specific Process Design Kit (PDK), which details the electrical and physical attributes of the manufacturing process and front-end building blocks (component libraries).

　　Supports multiple PDKs and circuit/electromagnetic (EM) co-simulation with a multi-technology design workflow for analyzing electrical interactions between bulk acoustic wave (BAW) and surface acoustic wave (SAW) filters (based on equivalent circuit models) and multilayer lamination packaging. It provides comprehensive module analysis and optimization. However, when developing silicon RFIC switches, low-noise amplifiers (LNAs), and PAs, the situation is different and requires more targeted development tools.

　　This article introduces a modern design workflow that converts PDK into a process that can be simulated within the NI AWR design platform to support chip packaging co-design and EM verification. By importing designs into dynamic libraries that can be used with PDKs, designers can effectively develop products based on different technologies using complex designs originally created in completely different environments.

　　EDA tools designed for specific needs

　　Designers use different RF EDA tools based on personal preferences and the capabilities of specific tools to handle individual or group design tasks. Some tools focus on high-frequency MMICs, PCBs, and module design, such as Microwave Office circuit design software. Other vendors, such as Cadence, are targeting silicon-based RFIC and module designs. Since each of these tools has its own advantages, it is best to adopt design flows that support interoperability and information exchange, so designers can select the best tools for each design task.

　　To support data exchange between different environments, several industry-standard file formats have been developed, such as touchstone (SNP) and Measurement Data Exchange Format (MDIF) files. The touchstone file provides S-parameters, which are small-signal analog or measured frequency responses of networks. MDIF files allow sorting of data such as S-parameters or noise using an unlimited number of independent variables (such as frequency or gate voltage). These formats allow designers to model the linear responses of devices (such as RFICs or switches) in their simulations and easily transfer the model back and forth between design tools.

　　The multiharmonic model (sometimes also called Keysight X parameters) is similar to S-parameters, increasing the ability to simulate nonlinear behavior under large-signal operating conditions. Other data formats used between different design tools include Spice netlists for circuit blocks, Exchange File Format (IFF) for schematic information, and layout formats such as GDSII and DXF.

　　These standard formats can be fully utilized, but each has its own limitations. For example, S-parameters are used for linear simulation and are not suitable for nonlinear simulation. Some RF simulators can only use dual-port MDIF files. Large-signal multiharmonic models may take a long time to generate and simulate, and files are often large and difficult to share. For the X parameter, the file can be gigabytes.

　　Challenges faced by module and subsystem designers

　　For RF modules that integrate multiple technologies developed using various tools, the complexity of the overall design task often means the demand for greater interoperability between tools often goes beyond simple data format compatibility. Front-end modules and other multi-technology devices can contain up to 25 integrated circuits on a single lamination module, including BAW and SAW filters, III-V RF MMIC PAs, as well as silicon switches and silicon LNAs with multiple antennas. In the design example presented here, silicon switches and LNAs are designed using Cadence tools, while acoustic/lamination filters are completed in Microwave Office software. Figure 1 shows a typical multi-chip module design.

　　RF Front-End Module Integration Design Flowchart 1 Based on Virtuoso and NI AWR Software 1: Typical module design in the Microwave Office software environment is very time-consuming for switch designers to create all the files required for the required switching states. This process can be prone to errors because it needs to support over 250 states covered by the RFIC. For touchstone files, only linear behavior is captured. For switches and even acoustic filters, critical nonlinear behavior needs to be captured by larger multiharmonic files. With RFIC analysis and S-parameter file generation, each state takes 7 minutes, while one switch operation has 68 states and another has 25 states, which requires a significant time investment. Typically, a single operation can take several hours or even days.

　　Cadence Virtuoso and NI AWR software co-simulate workflows

　　The solution introduced in this article leverages new features that support Cadence designs directly within Microwave Office software. Figure 2 shows this process. Here, the Microwave Office-based Spectre net-table conversion design process enables collaborative simulation between Virtuoso and NI AWR software.

　　Figure 2: Cadence Spectre conversion process for collaborative simulation in the NI AWR design platform Designers use silicon process PDKs and transfer them via Spectre design netlist to Microwave Office software, enabling designers to access all NI AWR design environment tools to achieve this process. These tools include Visual System Simulator (VSS) system design software, Microwave Office linear and nonlinear simulation, APLAC harmonic balancing and transient simulation, NI AWR layout tool, as well as AXIEM 3D plane and Analyst 3D finite-element method (FEM) EM simulators.

　　Figure 3 shows the Virtuoso schematic of a bipolar/eight-throw (DP8T) silicon switch with an on-chip filter. Its key component is the Antenna Switch Module (ASM), which has six different switching states.

　　Netlist and run

　　Use the "Netlist and Run" command to create the files required for NI AWR software conversion. Since this command runs on the test platform, the conversion is actually a subcircuit. The most critical file created is input.scs, which contains all relevant Cadence schematic information.

　　Running the "Import Spectre Netlist Design" script will open a simple user interface dialog. This switch design (about 2,000 netlists) takes about one second to translate. After translation, two components can be used in any design: one for the process and the other for the actual design.

　　A log file was also generated to provide designers and support teams with more detailed information about translated cells, libraries used, and test platform simulations. This conversion includes microstrip line (MLIN) elements from the original design, providing precise modeling of dispersion and loss in the transmission line in the design. Additionally, it captures the directory path of any file on the Cadence side containing the S-parameter block.

　　After the transfer switch design is complete, users load two new PDKs into new or existing projects in the Microwave Office software: the translated Cadence foundry PDK (csoi7RF Global Foundries PDK, see left side of Figure 4) and the design PDK (RF-Core, see right side of Figure 4). The RF Core file provides schematic elements and design blocks. These PDKs will provide three simple NI AWR software library elements needed for simulation.

　　Figure 4: Translated Cadence foundry PDK (left) and design PDK (right) appear in the element tree library, allowing insertion of any NI AWR software design new library element into the Microwave Office circuit design software schematic via standard drag-and-drop, just like any other schematic element. As shown in the schematic in Figure 5, the PROCESS block is used to reference the foundry's PDK process and allows users to modify process corners. Using the DESIGN block, users can access any design variable in Cadence design.

　　Figure 5: In this Microwave Office schematic, you can see the PROCESS block (foundry PDK process) and the DESIGN block of the design variables designed by Cadence. On the right side of the diagram, the translated component has about 20 ports. The DESIGN module controls the position of the switch state (set to 6 in this case) and controls the two voltages for the switch state. The PROCESS block in the upper left corner (highlighted on the left side of the diagram) gives designers the ability to specify process corners, which is very important for IC design.

　　To verify the frequency response of the simulated net-table conversion in Microwave Office and the original Spectre results, the S-parameters simulated by the test case Spectre were imported into Microwave Office for comparison. The verification settings are actually the same as those for schematic testbenches containing translated netlists. For this simulation, the subcircuit contains touchstone S parameter blocks directly derived from Cadence.

　　Compare small signal results

　　Figure 6 shows a comparison between the small-signal results simulated by NI AWR software and the Spectre results, represented by the S-parameters across the entire frequency band. As expected, the results showed that the two outcomes were exactly consistent.

　　Figure 6: Supplementary analysis comparing the small-signal results simulated by NI AWR software with Spectre results.

　　Design transitions have now been validated, and many other simulations can be performed using switches, including scanning process corners, adjusting/scanning switch status, and adjusting/scanning control voltage. The imported RFIC behaves like a regular Microwave Office element. On the left side of Figure 7, scanned process corners are compared with reference data directly obtained from Cadence, showing the impact of process corners and overlap between the simulator.

　　Figure 7: Other simulations can now be run using switches, as their behavior is similar to a regular Microwave Office element. The right side of Figure 7 shows the simulated insertion loss for different switch states (via path) in this example. The RFIC is controlled through six different switching states, showing different responses depending on the switching state. Designers can now develop laminate design details based on precise RFIC models, easily change states through parameter settings, and achieve adjustments or scanning.

　　Moreover, since the switch design is a conventional Microwave Office subcircuit, it can be combined with any other Microwave Office components, EM structures, data files, and so on. Multiple technologies can be combined into a single Microwave Office project, enabling cross-technology collaborative simulation and layout integration. A single stacked module can include and combine silicon switches, III-V PA FIC, acoustic filters, and more. The final integrated design layout includes acoustic filters, silicon devices, GaAs-PAs, and modules.

　　Distribution layout

　　Switch layouts can also be exported from Virtuoso in standard formats such as GDSII and imported into NI AWR software, then linked or linked to schematic subcircuits to ensure correct layout connections (see Figure 8). The geometric layout is the same, but the colors vary according to preference.

　　8: Switch layouts can be exported from Cadence Virtuoso and imported into NI AWR software, then linked or linked with schematic subcircuits to ensure correct layout connection conclusions.

　　This article introduces an integrated design process that combines multiple technologies derived from different software tools into a single project, enabling collaborative simulation between simulation and layout design tools. This process not only enables designers to integrate different semiconductor and packaging (lamination) technologies, but also leverages complex designs originally created in the RFIC design environment and integrates them into design environments specifically designed for MMIC, RF PCB, and module development. The final integrated design layout includes four different technologies: acoustic filters, silicon devices, GaAs PAs, and modules.